A. Field of the Invention
The invention relates to a differential charge pump circuit, and more particularly, to a differential charge pump circuit using a method of exchanging common mode current sources to decrease the influence of the mismatches between the common mode currents upon the duty cycle.
B. Description of the Related Art
In the applications of optical storage, the data patterns are embossed on the disk. The embossed pattern signals of the disk are read out by a photo detector and is translated into a voltage signal named RF signal. The RF signal are processed through an automatic gain control circuit, an equalizer circuit and a buffer circuit and then is fed to a slicer circuit to slice data as high or low. The signals after the slicer are bit stream patterns with 1 or 0. If the data “1” is weighted 1 and the data “0” is weighted −1, due to the data format of the disk, the digital sum value (DSV) is equal to 0 for long term. The total numbers of data “1” are equal to total numbers of data “0”. Due to the data's digital sum value is equal to 0, we can use a close-loop charge pump control system to set the optimum slicer level to acquire a zero digital sum value result.
A general charge pump circuit is a close-loop control system that has to overcome pre signal processing's offset so as to set up an optimum slicer level and to get a data string with digital sum value equal to 0. FIG. 1 shows a single-end charge pump 14 used in a single-end close loop system which sets up an optimize slicer level and then uses a trans-conductance circuit 12 to offset a dc current to the buffer 11 and to adjust the slicer level of the slicer 13. The slicer 13 is used to generate a comparison signal (output signal) to control the charge and discharge of the capacitor. Due to the digital sum value is equal to 0's disk format, when the close loop feedback system reaches its equilibrium state, the charging charge is equal to the discharging charge in the same one cycle. That is:Iup*X %=Idn*(100−X %),
wherein X is the percentage of data “1”, Iup is the current of the upper charging current source, and Idn is the current of the lower discharging current source. Thus, the the percentage of data “1” of the close loop system is:X=(Iup/(Iup+Idn))  (1)
If Iup=Idn, then X=50% and it means that the data bit streams with the same numbers of data “1” and data “0”. However, the slicing out signals with digital sum value equal to 0 can not be generated owing to that there are some mismatches between the currents Iup and Idn. In the semiconductor manufacturing processes. If the Iup is not equal to the Idn, then X will not equal to 50% and digital sum value will not equal to zero.
Consequently, a differential charge pump circuit as shown in FIG. 2 has been disclosed to solve the problem of current mismatches between the currents Iup and Idn. In this charge pump circuit 24, the charging and discharging actions are performed at both terminals of the floating capacitor C. In addition, the two terminals of the floating capacitor C are switched according to the output result (H or L) in order to compensate the problem of current mismatches between the upper charging and lower discharging current sources in single end charge pump circuits, such as the example shown in FIG. 1.
FIG. 3 shows the charge and discharge paths for the differential charge pump circuit in FIG. 2, wherein φH indicates that the controlled switch is ON when the slicer is H, while φL indicates that the controlled switch is ON when the slicer is L.
Once the differential charge pump circuit 24 is adopted, it is necessary to provide a common mode path between the two terminals of the floating capacitor C by a common-mode feed back unit 25 in order to set the common mode voltage at the two terminals of the floating capacitor C.
The right-hand common mode current ICMR and the left-hand common mode current ICML provide a common mode current path.
FIGS. 4(A) and 4(B) show the operation modes when the output of the slicer is H and L, respectively. These represent the two charge paths of FIG. 3. However, there will be some mismatches between ICMR and ICML in the semiconductor manufacturing processes. As shown in FIG. 4, it is assumed that the right-hand common mode current ICMR equals to K times of the left-hand common mode current ICML (due to process mismatch), and that ICM1 and ICM0 equal to the left-hand common mode currents ICML when the output of the slicer is H and L, respectively. Under this condition and assumption, the current flowing into the upper plate of the capacitor C equals to the current flowing out of the bottom plate of the capacitor. Therefore,I1=Iup+ICM−ICM1=Idn+KICM1  (2)I0=Iup+ICM−KICM0=Idn+ICM0  (3).
From the equations (2) and (3), ICM1=ICM0I1*X=I0*(1−X)  (4)(Iup+ICM−ICM1)*X=(Idn+ICM0)*(1−X)X=(Iup+ICM−KICM1)/(2Iup+2ICM−(1+K)ICM1)  (5)
If K=1, the left-hand and right-hand common mode currents fully match with each other, andX=50% (6)
It means the digital sum value is equal to 0. Accordingly, it can be proved from Equation (6) that the duty cycle X is independent of the current Iup and Idn when K=1. However, under the condition that K≠1 (i.e., the left-hand common mode current ICML is not equal to the right-hand common mode current ICMR, the duty cycle X still cannot be kept at 50%.
Although we can use differential charge pump circuit to overcome charge and discharge current mismatch issue, but if the common mode current path has mismatch, it still contributes to the close loop charge pump system and X still cannot be kept at 50%.